//***************************************************************************************
// Clock 3
// Use 32.768 KHz crystal for MCLK
//
// MSP430G2211
// Jed Margolin 2/27/2016.
// Built with Code Composer Studio v6
//***************************************************************************************
// main.c
#include <msp430.h>
//#include <msp430G2211.h>
#define TIME 6
void wait(unsigned int);
void wait2(void);
//================================================
int main(void)
{
volatile unsigned int k = 0;
WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer
wait(200); // give the crystal time to stabilize
P1SEL |= BIT0; // ACLK
// P1SEL2 &= ~(BIT0); // not used by msp430g2211
P1DIR |= BIT0;
P1SEL &= ~BIT1; // In
// P1SEL2 |= BIT1; // not used by msp430g2211
P1REN |= BIT1; // pullup/pulldown enabled
P1OUT |= BIT1; //
P1DIR &= ~(BIT1); //
P1SEL &= ~BIT2; // Out
// P1SEL2 |= BIT2; // not used by msp430g2211
P1DIR |= BIT2; //
P1SEL &= ~(BIT3); // Out - for testing
// P1SEL2 &= ~(BIT3); // not used by msp430g2211
P1DIR |= BIT3; //
P1SEL |= BIT4; // Out for SMCLK so we know it's working
// P1SEL2 &= ~(BIT4); // not used by msp430g2211
P1DIR |= BIT4; //
P1SEL &= ~(BIT5); // In
// P1SEL2 &= ~(BIT5); // not used by msp430g2211
P1REN |= BIT5; // pullup/pulldown enabled
P1OUT |= BIT5; // pullup
P1DIR &= ~(BIT5); //
P1SEL &= ~(BIT6); // Out
// P1SEL2 &= ~(BIT6); // not used by msp430g2211
P1DIR |= BIT6; // pullup
P1DIR &= ~(BIT7); // In - 60Hz phase
P1OUT |= BIT7; // pullup
P1SEL &= ~(BIT7); //
// P1SEL2 &= ~(BIT7); // not used by msp430g2211
P1REN |= BIT7; // pullup/pulldown enabled
// Enable the crystal
// BCSCTL1 comes out of reset with:
// XT2OFF = 1 (MSP430G2553 and MSP430G2211 don't have XT2)
// XTS = 0 (LFXT1 = Low Frequency mode)
// DIVAx = 0 (ACLK Divider = 1)
// RSELx = 7 (Range Select - should be for DCO only)
BCSCTL3 |= LFXT1S_0 + XCAP_3;
// LFXT1S = 0 (32768 crystal on LFXT1
// XCAP = 3 (12.5pF)
while(IFG1 & OFIFG) // OFIFG is Bit1 in IFG1 (Interrupt Flag Register)
// and means oscillator fault
{
IFG1 &= ~OFIFG; // keep resetting it until it doesn't need to be reset
wait2();
}
// We are going to leave SCG1 and SCG0 off
// _bis_SR_register(SCG1 + SCG0); // Set bits SCG1 and SCG0
// SCG1 (System Clock Generator 1) When set turns off the SMCLK
// SCG0 (System Clock Generator 0) When set turns off the DCO dc generator if DCOCLK is not used for MCLK or SMCLK
// We will leave DCO dc generator on just in case
BCSCTL2 = 0xC8;
// SELMx(7,6) = (1,1) Select MCLK = LFXT1CLK or VLOCLK
// DIVMx(5,4) = (0,0) MCLK Divider = /1
// SELS(3) = (1) SMCLK = LFXT1CLK or VLOCLK
// DIVSx(2,1) = (0,0) SMCLK Divider = /1
// DCOR(0) = (0) not used
// end of setup for crystal
//-----------------------
while (1) // main loop
{
P1OUT |= BIT6;
wait(TIME);
P1OUT &= ~(BIT6);
wait(TIME);
} // end main loop
} // end main
//==================================
void wait(unsigned int time)
{
volatile unsigned int i,j;
for(i=time; i>0; i--)
{
for(j=249; j>0; j--);
{
}
}
return;
} // end wait
//==========================================================
void wait2()
{
volatile unsigned int i;
for(i=0; i<48; i++){}
return;
} // end wait2
//========================================================