Fairchild came out with the first masked ROM in 1967. It was done in MOS, which was new for Fairchild, had 256 bits (64 x 4), and had an access time of 1 us. It was not a big hit because it was too small to store a sine/cosine lookup table and too slow to replace random logic. It also had a mask charge of $4,000.

Remember, in 1967 there were no microprocessors. A computer consisted of one or more processor boards, with one or more stacks of magnetic core memory.

In the case of Digital Equipment Corporation's PDP8, once the boot program was loaded in by the front  panel switches, everything else came in on paper tape or magnetic tape.

The only real use for masked ROM would be to free-up core that was used to store fixed tables, assuming masked ROM was cheap enough.

Fairchild and others kept working on masked ROM until they got it up to respectable size and speed.

In May, 1970, Radiation, Inc. came out with the first practical ROM that could be programmed by the user. This device used the bipolar process and was programmed by using high current pulses to burn open the appropriate interconnects in the metal layer. In order to make sure that the metal burned open in the right spot, the metal lines were narrowed where they were supposed to open; thereby earning the name 'fuses'. The first bipolar PROM (Programmable Read Only Memory) had 512 bits (64 x 8), had a very respectable access time of 65ns (which was blazingly fast for 1970), and cost $47 (100's) for the commercial version.

Radiation, Inc. started out by making high cost, high reliability ICs for the military. When they decided to enter the commercial/industrial market they changed their name to Harris Semiconductor to reflect their corporate parent, the Harris-Intertype Corporation.

Later in the year, Spectrum Dynamics came out with a programmer for Bipolar PROMs. The unit cost $945.

In 1971 Intel came out with the first memory that could be not only programmed by the user, but could be erased with ultraviolet light and programmed again. This was the 1702 EPROM. It was 2048 bits (256 x 8), used PMOS (which meant it was slow), required three voltages (+5V, +12V, and -12V) to operate, and each data line required a strobed -48V pulse for programming. But it worked. Each cell had two transistors: one with a floating gate to store 0 or 1 and one in the array that read it when addressed. This is the  data sheet for the 1702A (304KB PDF) that was made by National Semiconductor. While the 1702 used -12V for VGG, the 1702A used -9V.

The 1702 was introduced to the world in the May 10, 1971 issue of Electronics Magazine in an article written by Dov Frohman, the inventor of the EPROM. It contains a very curious paragraph:

    " Erasure, however, has to be accomplished by non-electrical methods,
      since the gate electrode is not accessible electrically. Shining ultraviolet
      light on any part of an unpackaged device causes a photocurrent to flow
      from the floating gate back to the silicon substrate, thereby discharging
      the gate to its initial, uncharged condition. This method of erasure allows
     complete testing and correction of a complex memory array before the
     package is finally sealed. Once the package is sealed, information can
     still be erased by exposing it to X radiation in excess of 5 X 10**4 rads,
     a dose which is easily attained with commercial X-ray generators."

X-rays? X-RAYS??

According to Dr. Frohman who was still working for Intel when I spoke to him in 1993, they ended up deciding to ship the part with a window because erasing the EPROM with X-rays created surface states in the silicon that required annealing. What this means is that the X-rays disrupted the crystal structure at the surface of the silicon which could be fixed by annealing in which sufficient thermal energy is supplied to the damaged layer of atoms so they can rearrange themselves. Since the underlying wafer is single-crystal, it serves as a seed for the epitaxial regrowth of the layer being treated. Generally, the required temperature is between 450 degrees Celsius and something less than the melting point of silicon which is 1410 degrees Celsius.

In other words, to erase your EPROM you would first have to X-ray it and then put it in an oven at about 600 degrees Celsius. The effects of this process on the reliability of the part would have required extensive testing so they decided on the window instead.

The wavelength of the ultraviolet light specified for erasing the EPROM was 254 nM. The reason for this is that UV fluorescent lamps of that wavelength were readily available because back then every barber placed his tools under a UV lamp to sterilize them between customers. Thus, UV lamps of the proper wavelength (called germicidal lamps) were available from your local barber supply house. Barbers do not generally use these lamps anymore but the lamps are used in water treatment plants and are popular in home spas.

A regular fluorescent lamp used for general lighting consists of a tube filled with low pressure mercury. Passing current through the mercury produces short wavelength ultraviolet energy. The inside of the tube is coated with a phosphor that is excited by the UV and emits visible light. To produce UV, just leave off the phosphor and use glass that does not block UV.

By the way, bug lights use long wavelength UV which is 365 nM.

In 1977 Intel announced the 2716 EPROM. This was a great improvement over the 1702A for several reasons:

     1. It was 2Kx8 instead of 256x8;

     2. It was NMOS and only needed +5V for normal Reads;

     3. The Programming voltage was +25V, was only on one pin, and was not strobed.

     4. For Programming, the data was presented to the data lines at TTL  levels, and
         the Programming Strobe was one pin, also at a TTL level.

     5. Each cell had only one transistor.
 

How Modern EPROMs Work

Each EPROM cell is an N-Channel MOS transistor with a floating gate, which means that the gate is not connected to anything. However, the gate is covered with another oxide layer (similar to the one between the gate and the substrate) and there is an additional gate called the Select gate deposited on top of this second oxide layer. See Figure 1.

VS for all cells is grounded. For a normal Read, VG is supplied from the row address decoder, VD is pulled up and goes to the sense amplifiers. All of the cells in a row are selected by the row address decoder and all of the cells in a column are connected to the sense amp for that column; only the cell at the intersection of the row and the column can pull the line low. (All of the other cells in that column go to rows that are not selected and therefore cannot be turned on.)

The floating gate is insulated so well that any charges that get into the capacitor formed in the oxide layer between the gate and the substrate stay there and do not leak away under normal circumstances. So how do we get the charges there in the first place, meaning, how do we program it?

To program a cell we apply a higher than normal voltage to the Select gate. (This is normally 12 Volts or higher, depending on the manufacturer.) The electrons flowing as a current between the drain and source of the saturated EPROM cell gain enough energy from the high electric field to jump the oxide barrier between the channel and the floating gate (see Figure 2). This process is called hot-electron injection.

The MOS threshold voltage, VTH (also called the gate threshold voltage), of an unprogrammed cell is about 1.0 to 2.0 Volts. Programming causes a cell to accumulate enough electrons to raise VTH to 6.5 to 9.0 Volts.

In Read mode, the row address decoding circuitry in the chip selects the desired cell by pulling the gate voltage of the cell to VCC. Since VCC is typically 4.5 to 5.5 Volts, an erased cell with a VTH = 1.5 V would be turned on while a programmed cell with a VTH=7.5 V would remain off.

If VCC is slowly raised to a voltage near the threshold voltage of a programmed EPROM cell, the cell would begin to conduct and would no longer appear to programmed. Therefore, during programming, the threshold voltage of each cell to be programmed has to be raised above the maximum VCC at which the EPROM is normally operated which is typically 5.5 Volts. In order to have a safe operating margin, VCC is raised above the normal operating voltage during programming; when the programmer reads the location to make sure it is programmed, it is reading it at a threshold higher than would be encountered during normal reads in your hardware. You wouldn't want stray noise to make reading your EPROM erratic.

Some manufacturers specify a VCC of 6.25 Volts during programming, others specify 6.5 Volts.

In byte-wide EPROMs the columns are electrically separated into at least eight sections. At one time, some were actually separated into more sections so that several bytes could be programmed at a time. (During Reads, the outputs still appeared to be byte-wide.)

EPROMs are erased by exposing it to short wavelength ultraviolet light (254 nM) which causes the stored charge to leak off by photoconduction. Normal sunlight contains some amount of energy at 254 nM so all EPROM manufacturers recommend that you cover the EPROM with an opaque label to prevent accidental erase, besides which you really should label your EPROMs so you know what you have programmed into it.

Supposedly an EPROM can be erased by leaving it in direct sunlight for two weeks. Regular fluorescent lamps contain some amount of energy at 254 nM. but it isn't much, otherwise we would all have really deep tans, since it is ultraviolet that causes the skin damage that results in what we call a tan. 254 nM is called short wavelength UV and is the wavelength of special fluorescent lamps which are called Germicidal lamps.

The UV lamps used in Bug Lights is long wavelength UV (365 nM) and although they are cheap, are not recommended for erasing EPROMs.

Speaking of labels. It is always a great disappointment to discover that one has plugged in one's EPROMs backwards. There is an industry standard :

When you can read the label, pin 1 is either up or to the left. This is shown in Figure 3.